1. Field of the Invention
The present invention relates to a jitter measuring circuit and, in particular, to a jitter measuring circuit that enables a user to measure jitter of a clock signal.
2. Description of the Related Art
A jitter characteristic of clocks used in digital circuits, known as cycle-to-cycle jitter, is becoming important in these years. Cycle-to-cycle jitter is the difference in length between successive clock cycles or deviation of clock cycle among successive clock signals. Unlike period jitter, which is defined as the variation of each absolute value of period compared with a reference clock signal, cycle-to-cycle jitter is defined as relative difference between successive clock cycles or deviation of clock cycle among successive clock signals. A technique for detecting cycle-to-cycle jitter is described in Japanese Patent Application Laid-Open No. 2001-309312. According to the technique, a plurality of phase-difference detecting circuits are used to detect the phase difference between a clock signal to be measured and a reference clock signal, and each of phase-difference detecting circuits has different characteristics of phase-difference detection time periods respectively. Variations in the phase differences detected by each of the phase difference detecting circuits are found to detect cycle-to-cycle jitter.
As LSI manufacturing processes become finer, the package density of LSIs is becoming increasingly higher and so are operating frequencies these years. A detrimental effect of the increasingly finer processes is increase of power consumption in LSIs. Another problem is malfunctions or performance degradation due to power supply noise. The power supply noise is generated by variations in power supply potential caused by current ON/OFF by operation of logic circuits that are operating in synchronization with clocks. In order to reduce consumption current, so-called clock gating is generally used that deactivates the clocks in logic circuits that are not performing operation processing. Although the technique is typically effective for reducing power consumption, it tends to increase power supply noise, which can cause malfunctions compared with cases where clock gating is not used, because current significantly changes each time clocks are deactivated and reactivated.
Power supply noise can cause malfunctions and performance degradation of circuits because of:    (1) increase of clock jitter, and    (2) increase of delay jitter in the logic circuits themselves.
These factors cause timing violations in the circuits. The factors (1) and (2) cannot be measured by the existing techniques. Therefore, in conventional circuit design methods, the factors (1) and (2) caused by power supply noise are empirically predicted and circuits are designed by allowing for these factors as design margins. Large margins must be set to avoid timing violations because the amounts of jitter cannot be known and the excessive margins have degraded the performance of LSIs.
The technique disclosed in Japanese Patent Application Laid-Open No. 2001-309312 detects cycle-to-cycle jitter. However, the technique does not measure the amount of the jitter. The technique compares a clock signal to be measured against a reference signal using a plurality of phase-difference detecting circuits. However, the technique does not take into consideration the influence of power supply noise on the reference signal. To detect jitter of a clock signal to be measured caused by power supply noise, the influence of power supply noise must be removed from the reference clock signal, which removal is difficult to implement. Furthermore, the technique disclosed in Japanese Patent Application No. 2001-30931 does not distinguish between the factors (1) and (2). Therefore, the amount of jitter caused by each factor cannot be determined.